The present invention relates to a semiconductor design technology, and more particularly, to an one-time-programmable cell having improved reliability, simple structure, reduced power consumption and a small size, and a memory device having the same.
An one-time programmable (OTP) cell is widely used for an integrated circuit (IC) chip as a single memory or a memory array. The OTP cell is especially used for marking an identification (ID), setting parameters, and controlling internal voltage level of a die or a chip. Therefore, the OTP cell and an OTP memory array greatly influence the yield and the characteristics of the IC chip.
The OTP cell and the OTP memory array are also used in an IC chip for a liquid crystal display (LCD) driver, for the same purpose as described above. The OTP cell and the OTP memory array are also used for assigning a dummy address for repairing/replacing a defective static random access memory (SRAM). Furthermore, recently, the OTP cell and the OTP memory array are frequently used for setting internal conditions of an LCD setting auto-sequence which is required by module manufacturers.
The OTP cell may be implemented with two basic states, fuse and anti-fuse.
A fuse method includes cutting a metal or poly resistance. That is, the fuse of the OTP cell is electrically short-circuited to have a minimum resistance in a normal state, but becomes open-circuited to have an infinitive resistance after cutting the metal or poly resistance. Manufacturing the OTP cell having the fuse needs a laser equipment for cutting the metal or poly resistance, and thus requires an increased manufacturing time and increased manufacturing costs. In addition, the metal or poly resistance may also be cut and short-circuited by external environments such as a temperature, which may degrade device reliability.
An anti-fuse device may be implemented with a gate oxide capacitor including a gate and a substrate of a complementary metal-oxide semiconductor (CMOS) transistor as electrodes. In a normal state, the capacitor has an infinitive resistance so that the anti-fuse is open-circuited. However, when high voltage VPP is applied to the gate or the substrate, the gate and the substrate become short-circuited so that the anti-fuse has a resistance ranging from ohms to tens of ohms. The resistance value ranging from ohms to tens of ohms indicates the gate insulation layer is broken.
As described above, in the case of the anti-fuse with a CMOS gate insulation layer, the resistance-cutting voltage is generated inside a circuit itself. Therefore, unlike the fuse method, the anti-fuse method does not need a laser equipment and is not influenced by time and temperature, which may enhance device reliability.
Hereinafter, a typical OTP cell with an anti-fuse will be described with reference to U.S. Pat. No. 6,927,997B2.
FIG. 1 is a circuit diagram of a typical OTP unit cell.
Referring to FIG. 1, the OTP cell includes an anti-fuse ANT_FS1, a switch SW1, and NMOS transistors NM1 and NM2. The anti-fuse ANT_FS1 is connected between a node A and a node B. The switch SW1 is connected between the node B and a ground voltage terminal. The NMOS transistor NM1 is connected between the node B and a node E via the NMOS transistor NM2 and has a gate connected to a node C. The NMOS transistor NM2 is connected between the source of the NMOS transistor NM1 and the node E and has a gate connected to a node D.
For reference, the NMOS transistor NM1 is a high-voltage MOS transistor for preventing a gate insulation layer of the NMOS transistor NM2 from the breakdown by the high voltage VPP.
Hereinafter, a method of writing data to and reading data from the typical OTP unit cell of FIG. 1 will be described with reference to Table 1 and FIGS. 2A and 2B.
nodemodeACDSW1write modeVPPLLONread modeVDDHHOFF
FIG. 2A illustrates an operation of the typical OTP unit cell of FIG. 1 in a write mode.
Referring to Table 1 and FIG. 2A, a high voltage VPP is applied to a node A. At the same time, a switch SW1 is turned on, and signals of a logic low level are applied to nodes C and D so that NMOS transistors NM1 and NM2 are turned off. Then, a current path is formed from the node A to the ground voltage terminal via the switch SW1. In other words, because a high voltage VPP is applied to a substrate and a gate of an anti-fuse ANT_FS1, the gate insulation layer is broken so that the anti-fuse ANT_FS1 may have a resistance ranging from a few ohms to tens of ohms.
FIG. 2B illustrates an operation of the typical OTP unit cell of FIG. 1 in a read mode.
Referring to Table 1 and FIG. 2B, an external voltage VDD is applied to the node A. At the same time, a switch SW1 is turned off, and signals of a logic high level are applied to the nodes C and D so that NMOS transistors NM1 and NM2 are turned on. Then, a current path is formed from the node A to the node E via the NMOS transistors NM1 and NM2.
The case when the anti-fuse ANT_FS1 is cut to output a data of a logic high level to the output node E will be described below. An external voltage VDD applied to the node A undergoes voltage drops by a resistance of from ohms to tens of ohms of the anti-fuse ANT_FS1, and by the turn-on resistances of the NMOS transistors NM1 and NM2 before being output through the node E. Because of the voltage drops at the anti-fuse ANT_FS1 and the NMOS transistors NM1 and NM2, a voltage of a level corresponding to the external voltage VDD is output through the node E.
The case when the anti-fuse ANT_FS1 is not cut so that a data of a logic low level is output to the output node E will be described below. In this case, the anti-fuse ANT_FS1 has an infinitive resistance because it is not cut. Therefore, the external voltage VDD applied to the node A undergoes voltage drops by an infinitive resistance of the anti-fuse ANT_FS1, and by the turn-on resistances of the NMOS transistors NM1 and NM2 before being output through the node E. Because of the voltage drops at the anti-fuse ANT_FS1 having an infinitive resistance, a voltage of a level corresponding to the ground voltage is output through the node E.
Though not shown in FIGS. 1 through 2B, the data output from the node E is sensed and amplified by a differential amplifier.
An OTP memory device including a plurality of the OTP unit cells of FIG. 1 will be described with reference to FIG. 3.
FIG. 3 is a block diagram of a typical OTP memory device.
Referring to FIG. 3, the OTP memory device includes a plurality of first read-control lines RD_CTRL1<0:N>, a plurality of second read-control lines RD_CTRL2<0:N>, a plurality of write-control lines WR_CTRL<0:N>, a plurality of OTP unit cells 10, a plurality of data lines BL0 to BLn, a plurality of sense amplifiers 20, and a high voltage supply 30. The first and second read-control lines RD_CTRL1<0:N> and RD_CTRL2<0:N> extend in row direction and each of them is activated when a corresponding address is applied in a read mode. The write control lines WR_CTRL<0:N> extend in row direction and each of them is activated when a corresponding address is applied in a write mode. The OTP cells 10 are connected to the respective first read-control lines RD_CTRL1<0:N>, the respective second read-control lines RD_CTRL2<0:N>, and the respective write-control lines WR_CTRL<0:N>. The data lines BL0 to BLn extend in column direction to transfer output data from the OTP unit cells 10. The sense amplifiers 20 sense and amplify data received through the respective data lines BL0 to BLn. The high voltage supply 30 applies high voltage VPP to the OTP cells 10.
For reference, the sense amplifier 20 is implemented with a differential amplifier.
The complicated process for cutting the anti-fuse to write a data may increase access time. Furthermore, use of the differential amplifier as the sense amplifier may result in an additional current consumption by a bias terminal and an increased size of the memory device.